This invention relates to a comparator device and more particularly to a comparator device provided as a whole with fewer input terminals for comparison base bit signals than for bit signals being compared.
The prior art comparator device has an arrangement shown, for example, in FIG. 1. The section of FIG. 1 enclosed in broken lines represents a comparator device 1. With this comparator device 1, for example, seven bit signals being compared are transmitted through signal lines B0, B1, B2, B3, B4, B5, B6 to the corresponding seven input terminals P0, P1, P2, P3, P4, P5, P6. Seven input terminals of a comparison base signal S0, S1, S2, S3, S4, S5, S6 are supplied with seven bit signals Z0, Z1, Z2, Z3, Z4, Z5, Z6 collectively forming a comparison base signal Z. Namely, bit-to-bit comparison is made between bit signals being compared and comparison base bit signals. The input terminals P0 to P6 of seven bit signals being compared are connected to one input terminal each of seven coincidence circuits 2-0, 2-1, 2-2, 2-3, 2-4, 2-5, 2-6. The input terminals S0 to S6 of seven comparison base bit signals are connected to the other input terminal each of said seven coincidence circuits 2-0 to 2-6. The output terminals of the coincidence circuits 2-0 to 2-6 are connected to the corresponding input terminals of a seven input terminal-type AND circuit 3. An output signal from said AND circuit 3 is delivered to the output terminal 4 of the comparator device 1. Where the input terminal corresponding to any bit signal being compared and the corresponding input terminal of a comparison base bit signal are simultaneously supplied with a signal of the same logical level 0 or 1, then each of the coincidence circuits 2-0 to 2-6 generates a signal 1. And where said both input terminals are simultaneously supplied with bit signals of different logical levels, then the coincidence circuit gives forth a signal 0. For instance, where the bits Z0 to Z6 of the comparison base signal are chosen to have logical levels (1, 1, 1, 1, 0, 0, 0) respectively and, under this condition, the input terminals P0 to P6 of bit signals being compared are supplied with bit signals having the logical levels (1, 1, 1, 1, 0, 0, 0), then all the coincidence circuits 2-0 to 2-6 produce an output signal 1. As the result, the AND circuit 3 delivers a coincidence detection signal to the output terminal 4. On the other hand, where any of the bit signals delivered from the coincidence circuits 2-0 to 2-6 to the AND circuit 3 has a logical level 0, then said AND circuit 3 gives forth an output signal 0, showing that noncoincidence occurs between the bit signals being compared and comparison base bit signals. As mentioned above, the prior art comparator had to be provided with the same number of input terminals for comparison base bit signals as those for bit signals being compared.
However, the recent tendency is directed toward the integration or large scale integration of a comparator device to render it more compact and reliable. Since the presence of numerous terminals obstructs these forms of integration, demand is made to decrease the number of terminals as much as possible. For example, where an attempt is made to integrate the circuitry of the prior art comparator device of FIG. 1, seven input terminals for seven bit signals being compared, seven input terminals for seven comparison base bit signals and one output terminal of the comparator device, that is, fifteen terminals in all (excluding a power supply terminal) have to be taken into account. Since, the prior art comparator device needs the same number of input terminals for comparison base bit signals as those for bit signals being compared, integration of said comparator device is more handicapped as bit signals being compared increase in number.